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About NSL
About us
Company Profile
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Message from Chairman
Support
NSL Core command line options
NSL Sample
Beginners
1 input single gate BUF logic
BUF.nsl
BUF.v
1 input single gate inverter logic
INV.nsl
INV.v
15word x 8bit width synchronous FIFO sample
RAM_FIFO.nsl
RAM_FIFO.v
1bit F/F sample with asynchronous reset
FF_1bit_AR.nsl
FF_1bit_AR.v
1bit F/F sample with synchronous reset.
FF_1bit_SR.nsl
FF_1bit_SR.v
1bit Hi-Z IN/OUT bidirection I/O
HiZ_bidirect_1bit.nsl
HiZ_bidirect_1bit.v
1bit Hi-Z IN/OUT single direction I/O
HiZ_SinglePin_INOUT.nsl
HiZ_SinglePin_INOUT.v
1bit Hi-Z OUTPUT single direction I/O
HiZ_SinglePin_OUT.nsl
HiZ_SinglePin_OUT.v
2 input AND gate
AND2.nsl
AND2.v
2 input Exclusive NOR gate
ExNOR2.nsl
ExNOR2.v
2 input Exclusive OR gate
ExOR2.nsl
ExOR2.v
2 input NOR gate
NOR2.nsl
NOR2.v
2 input OR gate
OR2.nsl
OR2.v
3 input AND – OR gate
AOI.nsl
AOI.v
3 input MAJORITY combination logic
MAJORITY3.nsl
MAJORITY3.v
3 input OR – AND gate
OAI.nsl
OAI.v
3-STATE Octal Bus Transceiver Type-A
TTL74245_TypeA.nsl
TTL74245_TypeA.v
3-STATE Octal Bus Transceiver Type-B
TTL74245_TypeB.nsl
TTL74245_TypeB.v
3-STATE Octal Bus Transceiver Type-C
TTL74245_TypeC.nsl
TTL74245_TypeC.v
4bit binary counter
CNT4.nsl
CNT4.v
4bit F/F sample with AR ( Databus sample )
FF_4bit_AR.nsl
FF_4bit_AR.v
4bit F/F sample with SR ( Databus sample )
FF_4bit_SR.nsl
FF_4bit_SR.v
8bit binary counter ( 4bit counter x 2 instanciated )
CNT8_instance.nsl
CNT8_instance.v
8word x 8bit width PROM sample
RAM_PROM.nsl
RAM_PROM.v
8word x 8bit width SRAM(Memory array) sample
RAM_SRAM.nsl
RAM_SRAM.v
NSL code to Verilog code parameter passing
Middle
Function
Tutorial
00. NSL outline
01. I/O structure element
02. Internal terminal and register
03. Action description
04. Control terminal
05. Submodule
06. Procedure
07. State variable
08. Memory
09. Interface
10. System task
11. Directive
12.Structure
About NSL
About us
Company Profile
Directors
Message from Chairman
Support
NSL Core command line options
NSL Sample
Beginners
1 input single gate BUF logic
BUF.nsl
BUF.v
1 input single gate inverter logic
INV.nsl
INV.v
15word x 8bit width synchronous FIFO sample
RAM_FIFO.nsl
RAM_FIFO.v
1bit F/F sample with asynchronous reset
FF_1bit_AR.nsl
FF_1bit_AR.v
1bit F/F sample with synchronous reset.
FF_1bit_SR.nsl
FF_1bit_SR.v
1bit Hi-Z IN/OUT bidirection I/O
HiZ_bidirect_1bit.nsl
HiZ_bidirect_1bit.v
1bit Hi-Z IN/OUT single direction I/O
HiZ_SinglePin_INOUT.nsl
HiZ_SinglePin_INOUT.v
1bit Hi-Z OUTPUT single direction I/O
HiZ_SinglePin_OUT.nsl
HiZ_SinglePin_OUT.v
2 input AND gate
AND2.nsl
AND2.v
2 input Exclusive NOR gate
ExNOR2.nsl
ExNOR2.v
2 input Exclusive OR gate
ExOR2.nsl
ExOR2.v
2 input NOR gate
NOR2.nsl
NOR2.v
2 input OR gate
OR2.nsl
OR2.v
3 input AND – OR gate
AOI.nsl
AOI.v
3 input MAJORITY combination logic
MAJORITY3.nsl
MAJORITY3.v
3 input OR – AND gate
OAI.nsl
OAI.v
3-STATE Octal Bus Transceiver Type-A
TTL74245_TypeA.nsl
TTL74245_TypeA.v
3-STATE Octal Bus Transceiver Type-B
TTL74245_TypeB.nsl
TTL74245_TypeB.v
3-STATE Octal Bus Transceiver Type-C
TTL74245_TypeC.nsl
TTL74245_TypeC.v
4bit binary counter
CNT4.nsl
CNT4.v
4bit F/F sample with AR ( Databus sample )
FF_4bit_AR.nsl
FF_4bit_AR.v
4bit F/F sample with SR ( Databus sample )
FF_4bit_SR.nsl
FF_4bit_SR.v
8bit binary counter ( 4bit counter x 2 instanciated )
CNT8_instance.nsl
CNT8_instance.v
8word x 8bit width PROM sample
RAM_PROM.nsl
RAM_PROM.v
8word x 8bit width SRAM(Memory array) sample
RAM_SRAM.nsl
RAM_SRAM.v
NSL code to Verilog code parameter passing
Middle
Function
Tutorial
00. NSL outline
01. I/O structure element
02. Internal terminal and register
03. Action description
04. Control terminal
05. Submodule
06. Procedure
07. State variable
08. Memory
09. Interface
10. System task
11. Directive
12.Structure
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2024年9月24日
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