NSL Samples for beginners

• 1 input single gate BUF logic
  • BUF.nsl
  • BUF.v
• 1 input single gate inverter logic
  • INV.nsl
  • INV.v
• 15word x 8bit width synchronous FIFO sample
  • RAM_FIFO.nsl
  • RAM_FIFO.v
• 16bit parity generator
  • PAR16.nsl
  • PAR16.v
• 1bit F/F sample with asynchronous reset
  • FF_1bit_AR.nsl
  • FF_1bit_AR.v
• 1bit F/F sample with synchronous reset.
  • FF_1bit_SR.nsl
  • FF_1bit_SR.v
• 1bit Hi-Z IN/OUT bidirection I/O
  • HiZ_bidirect_1bit.nsl
  • HiZ_bidirect_1bit.v
• 1bit Hi-Z IN/OUT single direction I/O
  • HiZ_SinglePin_INOUT.nsl
  • HiZ_SinglePin_INOUT.v
• 1bit Hi-Z OUTPUT single direction I/O
  • HiZ_SinglePin_OUT.nsl
  • HiZ_SinglePin_OUT.v
• 2 input AND gate
  • AND2.nsl
  • AND2.v
• 2 input Exclusive NOR gate
  • ExNOR2.nsl
  • ExNOR2.v
• 2 input Exclusive OR gate
  • ExOR2.nsl
  • ExOR2.v
• 2 input NOR gate
  • NOR2.nsl
  • NOR2.v
• 2 input OR gate
  • OR2.nsl
  • OR2.v
• 3 input AND – OR gate
  • AOI.nsl
  • AOI.v
• 3 input MAJORITY combination logic
  • MAJORITY3.nsl
  • MAJORITY3.v
• 3 input OR – AND gate
  • OAI.nsl
  • OAI.v
• 3-STATE Octal Bus Transceiver Type-A
  • TTL74245_TypeA.nsl
  • TTL74245_TypeA.v
• 3-STATE Octal Bus Transceiver Type-B
  • TTL74245_TypeB.nsl
  • TTL74245_TypeB.v
• 3-STATE Octal Bus Transceiver Type-C
  • TTL74245_TypeC.nsl
  • TTL74245_TypeC.v
• 32bit parity generator
  • PAR32.nsl
  • PAR32.v
• 4bit adder. Hierarchy design.
  • ADDER4_func_call.nsl
  • ADDER4_func_call.v
• 4bit asynchronous adder
  • ADDER4_async.nsl
  • ADDER4_async.v
• 4bit binary counter
  • CNT4.nsl
  • CNT4.v
• 4bit F/F sample with AR ( Databus sample )
  • FF_4bit_AR.nsl
  • FF_4bit_AR.v
• 4bit F/F sample with SR ( Databus sample )
  • FF_4bit_SR.nsl
  • FF_4bit_SR.v
• 4bit synchronous adder
  • ADDER4_sync.nsl
  • ADDER4_sync.v
• 8bit binary counter ( 4bit counter x 2 instanciated )
  • CNT8_instance.nsl
  • CNT8_instance.v
• 8bit parity generator
  • PAR8.nsl
  • PAR8.v
• 8word x 8bit width PROM sample
  • RAM_PROM.nsl
  • RAM_PROM.v
• 8word x 8bit width SRAM(Memory array) sample
  • RAM_SRAM.nsl
  • RAM_SRAM.v
• IF statement variety code
  • IF Statement.nsl
  • IF Statement.v
• NSL code to Verilog code parameter passing
• Sequential operation example of 4bit by 4bit multiply function
  • func_seq_test.nsl
  • func_seq_test.v