This is a list of NSL description samples by function. You can download, view, and use them for free.

category	Function	Individual Features	Function Description	Down- load
Peripheral I/O Functions	Error detection (checksum) circuit	CRC16	This is a 16-bit data length cyclic redundancy check circuit module used as an error detection code. The generator polynomial is set to 0x1021, which is specified by CRC-16-CCITT, as the default value, but other generator polynomials can be used by changing the parameter declaration section in the NSL source code.
Peripheral I/O Functions	Error detection (checksum) circuit	CRC32	This is a 32-bit data length cyclic redundancy check circuit module used as an error detection code. The generator polynomial is set to 0×04C11DB7, which is specified in CRC-32-IEEE 802.3, as the default value, but other generator polynomials can be used by changing the parameter declaration section in the NSL source code.
Multimedia	Video / Image	YUV -> RGB	It generates RGB-8/8/8 pixel information from YUV signals (8-bit full scale) based on CCIR-601.1.
Multimedia	Video / Image	RGB -> YUV	It generates YUV signals (8-bit full scale) from RGB-8/8/8 pixel information based on CCIR-601.1.
Multimedia	Video / Image	YCbCr -> RGB	It generates RGB-8/8/8 pixel information from YCbCr signals (8-bit full scale) based on CCIR-601.1.
Multimedia	Video / Image	RGB -> YCbCr	It generates YCbCr signals (8-bit full scale) from RGB-8/8/8 pixel information based on CCIR-601.1.
Numerical Processing	Floating-point arithmetic	Adder-1 (Reference Design)	This is a 32-bit single-precision floating-point arithmetic circuit sample. It is a cycle-based adder, and the format is based on IEEE 754 single precision. The source has been divided so that it can be synthesized even with the 500-line limit of unlicensed NSL Core. Also, since this source code was created to understand the operation of floating-point arithmetic, a simulation model is not included.
Numerical Processing	Floating-point arithmetic	Subtractor-1 (Reference Design)	This is a 32-bit single-precision floating-point arithmetic circuit sample. It is a cycle-based adder, and the format is based on IEEE 754 single precision. The source has been divided so that it can be synthesized even with the 500-line limit of unlicensed NSL Core. Also, since this source code was created to understand the operation of floating-point arithmetic, a simulation model is not included.