機能

2input AND gate

信号機能

A_i ＝　入力信号A
B_i ＝　入力信号B
Q_o ＝　出力

記述特徴

NSL記述例

/* ************************************************************ */
declare AND2 {

    input       A_i ;
    input       B_i ;

    output      Q_o ;

}

/* ************************************************************ */
// Declare module
module AND2 {
/* ************************************************************ */
// Internal operation signals

/* ************************************************************ */
// Equation

    {
        Q_o = A_i & B_i ;
    }
}
/* ************************************************************ */

Verilog変換例

/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 19:50:36 2010
 Licensed to :NON PROFIT USER:
*/

module AND2 ( p_reset , m_clock , A_i , B_i , Q_o );
  input p_reset, m_clock;
  input A_i;
  input B_i;
  output Q_o;

   assign  Q_o = A_i&B_i;
endmodule
/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 19:50:36 2010
 Licensed to
*/