機能

8ビットパリティジェネレータ

信号機能

Data_i[8] ＝　8ビット幅の入力信号

Parity_o1 ＝　出力信号
Parity_o2 ＝　出力信号

解説

記述特徴

Parity_o1は，排他的論理和演算子を各ビットに対して使用．
Parity_o2は，排他的論理和演算子をリダイレクト構文に対して使用．

NSL記述例

/* ************************************************************ */
declare PAR8 {

    input       Data_i[8] ;

    output      Parity_o1 ;
    output      Parity_o2 ;

}

/* ************************************************************ */
// Declare module
module PAR8 {

/* ************************************************************ */
// Internal operation signals

/* ************************************************************ */
// Equation

    {
    //  Syntax Example #1
        Parity_o1 = {
            Data_i[7] ^ Data_i[6] ^ Data_i[5] ^ Data_i[4] ^
            Data_i[3] ^ Data_i[2] ^ Data_i[1] ^ Data_i[0]
        } ;

    //  Syntax Example #1
        Parity_o2 = ^( Data_i[7:0] ) ;

    }
}
/* ************************************************************ */

Verilog変換例

/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:55:24 2010

 Licensed to :EVALUATION USER:
*/

module PAR8 ( p_reset , m_clock , Data_i , Parity_o1 , Parity_o2 );
  input p_reset, m_clock;
  input [7:0] Data_i;
  output Parity_o1;
  output Parity_o2;

   assign  Parity_o1 = {(((((((Data_i[7])^(Data_i[6]))^(Data_i[5]))^(Data_i[4]))^(Data_i[3]))^(Data_i[2]))^(Data_i[1]))^(Data_i[0])};
   assign  Parity_o2 = ^(Data_i[7:0]);
endmodule
/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:55:24 2010

 Licensed to
*/