機能

16ビットパリティジェネレータ

信号機能

Data_i[16] ＝　16ビット幅の入力信号

Parity_o1 ＝　出力信号
Parity_o2 ＝　出力信号

記述特徴

Parity_o1は，排他的論理和演算子を各ビットに対して使用．
Parity_o2は，排他的論理和演算子をリダイレクト構文に対して使用．

NSL記述例

/* ************************************************************ */
declare PAR16 {

    input       Data_i[16] ;

    output      Parity_o1 ;
    output      Parity_o2 ;

}

/* ************************************************************ */
// Declare module
module PAR16 {

/* ************************************************************ */
// Internal operation signals
    wire    tmp_Parity_o1 ;
    wire    tmp_Parity_o2 ;

/* ************************************************************ */
// Equation

    {
    // Example statement #1
        tmp_Parity_o1 = {
            Data_i[7] ^ Data_i[6] ^ Data_i[5] ^ Data_i[4] ^
            Data_i[3] ^ Data_i[2] ^ Data_i[1] ^ Data_i[0]
        } ;
        tmp_Parity_o2 = {
            Data_i[15] ^ Data_i[14] ^ Data_i[13] ^ Data_i[12] ^
            Data_i[11] ^ Data_i[10] ^ Data_i[9] ^ Data_i[8]
        } ;

        Parity_o1 = tmp_Parity_o1 ^ tmp_Parity_o2  ;  

    // Example statement #2
        Parity_o2 = ^( Data_i[15:0] ) ;
    }
}
/* ************************************************************ */

Verilog変換例

/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:55:28 2010

 Licensed to :EVALUATION USER:
*/

module PAR16 ( p_reset , m_clock , Data_i , Parity_o1 , Parity_o2 );
  input p_reset, m_clock;
  input [15:0] Data_i;
  output Parity_o1;
  output Parity_o2;
  wire tmp_Parity_o1;
  wire tmp_Parity_o2;

   assign  tmp_Parity_o1 = {(((((((Data_i[7])^(Data_i[6]))^(Data_i[5]))^(Data_i[4]))^(Data_i[3]))^(Data_i[2]))^(Data_i[1]))^(Data_i[0])};
   assign  tmp_Parity_o2 = {(((((((Data_i[15])^(Data_i[14]))^(Data_i[13]))^(Data_i[12]))^(Data_i[11]))^(Data_i[10]))^(Data_i[9]))^(Data_i[8])};
   assign  Parity_o1 = tmp_Parity_o1^tmp_Parity_o2;
   assign  Parity_o2 = ^(Data_i[15:0]);
endmodule
/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:55:28 2010

 Licensed to
*/