機能

同期式4ビット加算器

信号機能

A_in[4] = 加算値
B_in[4] = 加算値
Q_out[4] = 結果出力

解説

A_inの値とB_inの値を加算し，Q_outに出力します。
テンポラリのレジスタとして’reg_Q[4]‘を定義しています。

NSL記述例

/* ************************************************************ */
declare ADDER4_sync {

    input       A_in[4] ;           // Add value input. Port-A
    input       B_in[4] ;           // Add value input. Port-B
    output      Q_out[4] ;          // Add result out

    func_in     exec( A_in, B_in ) ;// Add function execution request with parameter.
    func_out    done( Q_out ) ;     // Add function complete acknowledge with parameter.

}

/* ************************************************************ */
// Declare module
module ADDER4_sync {
    reg         reg_Q[4] = 4'b0000 ;// Declare register with initial value.

    proc_name   adder_finish(reg_Q) ;

/* ************************************************************ */
// Internal operation signals
//  {
//      Q_out   = reg_Q ;
//  }

/* ************************************************************ */
// Pallarel equation

/* ************************************************************ */
// Function independent equation
    func    exec {
        reg_Q := A_in + B_in ;
        adder_finish() ;
    }

    proc    adder_finish {
        done(reg_Q) ;
        finish ;
    }

}
/* ************************************************************ */

Verilog変換例

/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:53:17 2010

 Licensed to :EVALUATION USER:
*/

module ADDER4_sync ( p_reset , m_clock , A_in , B_in , Q_out , exec , done );
  input p_reset, m_clock;
  input [3:0] A_in;
  input [3:0] B_in;
  output [3:0] Q_out;
  input exec;
  output done;
  reg [3:0] reg_Q;
  reg adder_finish;
  wire _proc_adder_finish_set;
  wire _proc_adder_finish_reset;

   assign  _proc_adder_finish_set = exec;
   assign  _proc_adder_finish_reset = adder_finish;
   assign  Q_out =
//synthesis translate_off
(adder_finish)?
//synthesis translate_on
((adder_finish)?reg_Q:4'b0)
//synthesis translate_off
:4'bx
//synthesis translate_on
;
   assign  done = adder_finish;
always @(posedge m_clock or posedge p_reset)
  begin
if (p_reset)
     reg_Q <= 4'b0000;
else if (exec)
      reg_Q <= (A_in)+(B_in);
end
always @(posedge m_clock or posedge p_reset)
  begin
if (p_reset)
     adder_finish <= 1'b0;
else if (_proc_adder_finish_set|_proc_adder_finish_reset)
      adder_finish <= _proc_adder_finish_set;
end
endmodule
/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:53:17 2010

 Licensed to
*/