機能

8ビット同期式カウンタ回路
– 非同期リセット
– キャリ入力
– 初期値入力
– カウント有効
– キャリ出力

信号機能

PARAM_in[8] = 初期値
LOAD_in = 初期値ロード要求
ENB_in = カウント有効

Q_out[8] = データ出力信号

解説

本回路は，#includeと下位階層を扱う方法のサンプルコードです．

4ビット同期式カウンタ回路：CNT4.nslを2つ用いて，8ビットの同期式カウンタを構築します．
2個のCNT4.nslは，この回路内では下位階層のモジュールとして扱われます．
このことをインスタンシエート(instanciate）と呼びます．
4ビットカウンタ自身の動作は別途CNT4.nslを参照してください．

NSL記述例

/* ************************************************************ */
#include    "CNT4.nsl"      // Instanciate lower module

/* ************************************************************ */
declare CNT8_instanciate {

    input       PARAM_in[8] ;   // Initial parameter．
    input       LOAD_in ;       // Synchronous PARAM_in load request.
    input       ENB_in ;        // Count enable

    output      Q_out[8] ;      // Flip-Flop data output
    func_out    CARRY_out() ;   // Carry-output at internal counter is all-H.

}

/* ************************************************************ */
// Declare module
module CNT8_instanciate {

/* ************************************************************ */
// Instanciate lower-module
    CNT4    lower_CNT4 ;            // Instanciate CNT[3:0]
    CNT4    upper_CNT4 ;            // Instanciate CNT[7:4]

/* ************************************************************ */
// Internal operation signals

/* ************************************************************ */
// Pallarel operation equation

    {
    // Lower 4bit counter
        lower_CNT4.PARAM_in     = PARAM_in[3:0] ;
        lower_CNT4.LOAD_in      = LOAD_in ;
        lower_CNT4.ENB_in       = ENB_in ;

        lower_CNT4.CARRY_in() ;
                    // -> Call lower 4bit counter carry-in() procedure.

    // Upper 4bit counter
        upper_CNT4.PARAM_in     = PARAM_in[7:4] ;
        upper_CNT4.LOAD_in      = LOAD_in ;
        upper_CNT4.ENB_in       = ENB_in ;

        if ( lower_CNT4.CARRY_out ) {
                    // Check lower 4bit counter value is %1111 ( Carry-up )
            upper_CNT4.CARRY_in() ;
                    // -> Call upper 4bit counter carry-in() procedure.
        }

    // Output signals
        Q_out   = { upper_CNT4.Q_out , lower_CNT4.Q_out } ;
                                    // 4bit + 4bit => 8bit bus width.

    // Generate CARRY-OUT to more higher counter.
        if ( upper_CNT4.CARRY_out & lower_CNT4.CARRY_out ) {
            CARRY_out() ;
        }

    }

}
/* ************************************************************ */

Verilog変換例

/*
 Produced by NSL Core, IP ARCH, Inc. Tue Jun 08 16:34:01 2010
 Licensed to :NON PROFIT USER:
*/

module CNT4 ( p_reset , m_clock , PARAM_in , LOAD_in , ENB_in , CARRY_in , Q_out , CARRY_out );
  input p_reset, m_clock;
  input [3:0] PARAM_in;
  input LOAD_in;
  input ENB_in;
  input CARRY_in;
  output [3:0] Q_out;
  output CARRY_out;
  reg [3:0] Counter_4bit;
  wire _net_0;
  wire _net_1;

   assign  _net_0 = (Counter_4bit)==(4'b1111);
   assign  _net_1 = CARRY_in&ENB_in;
   assign  Q_out = Counter_4bit;
   assign  CARRY_out = _net_0;
always @(posedge m_clock)
  begin
if ((_net_1)|(LOAD_in))
      Counter_4bit <= ((_net_1) ?(Counter_4bit)+(4'b0001):4'b0)|
    ((LOAD_in) ?PARAM_in:4'b0);

end
endmodule
/*
 Produced by NSL Core, IP ARCH, Inc. Tue Jun 08 16:34:01 2010
 Licensed to
*/

module CNT8_instanciate ( p_reset , m_clock , PARAM_in , LOAD_in , ENB_in , Q_out , CARRY_out );
  input p_reset, m_clock;
  input [7:0] PARAM_in;
  input LOAD_in;
  input ENB_in;
  output [7:0] Q_out;
  output CARRY_out;
  wire _lower_CNT4_CARRY_out;
  wire [3:0] _lower_CNT4_Q_out;
  wire _lower_CNT4_CARRY_in;
  wire _lower_CNT4_ENB_in;
  wire _lower_CNT4_LOAD_in;
  wire [3:0] _lower_CNT4_PARAM_in;
  wire _upper_CNT4_CARRY_out;
  wire [3:0] _upper_CNT4_Q_out;
  wire _upper_CNT4_CARRY_in;
  wire _upper_CNT4_ENB_in;
  wire _upper_CNT4_LOAD_in;
  wire [3:0] _upper_CNT4_PARAM_in;
  wire _net_2;
  wire _net_3;
CNT4 upper_CNT4 (.p_reset(p_reset), .m_clock(m_clock), .CARRY_out(_upper_CNT4_CARRY_out), .Q_out(_upper_CNT4_Q_out), .CARRY_in(_upper_CNT4_CARRY_in), .ENB_in(_upper_CNT4_ENB_in), .LOAD_in(_upper_CNT4_LOAD_in), .PARAM_in(_upper_CNT4_PARAM_in));
CNT4 lower_CNT4 (.p_reset(p_reset), .m_clock(m_clock), .CARRY_out(_lower_CNT4_CARRY_out), .Q_out(_lower_CNT4_Q_out), .CARRY_in(_lower_CNT4_CARRY_in), .ENB_in(_lower_CNT4_ENB_in), .LOAD_in(_lower_CNT4_LOAD_in), .PARAM_in(_lower_CNT4_PARAM_in));

   assign  _lower_CNT4_CARRY_in = 1'b1;
   assign  _lower_CNT4_ENB_in = ENB_in;
   assign  _lower_CNT4_LOAD_in = LOAD_in;
   assign  _lower_CNT4_PARAM_in = PARAM_in[3:0];
   assign  _upper_CNT4_CARRY_in = _net_2;
   assign  _upper_CNT4_ENB_in = ENB_in;
   assign  _upper_CNT4_LOAD_in = LOAD_in;
   assign  _upper_CNT4_PARAM_in = PARAM_in[7:4];
   assign  _net_2 = _lower_CNT4_CARRY_out;
   assign  _net_3 = (_upper_CNT4_CARRY_out)&(_lower_CNT4_CARRY_out);
   assign  Q_out = {_upper_CNT4_Q_out,_lower_CNT4_Q_out};
   assign  CARRY_out = _net_3;
endmodule
/*
 Produced by NSL Core, IP ARCH, Inc. Tue Jun 08 16:34:02 2010
 Licensed to
*/