機能

4ビット加算器　/　ファンクションコール方式

信号機能

_in[4] = 加算値
B_in[4] = 加算値
Q_out[4] = 結果出力

解説

A_inの値とB_inの値を加算し，Q_outに出力します．
可算回路を下位階層モジュールに定義し，上位モジュールから加算を行なうにあたって制御入力信号のコールを行います．

NSL記述例

/* ************************************************************ */
declare adder4 {

    input       A_in[4] ;           // Add value input. Port-A
    input       B_in[4] ;           // Add value input. Port-B
    output      Q_out[4] ;          // Add result out

    func_in exec( A_in, B_in ) ;    // Add function execution request with parameter.
    func_out    done( Q_out ) ;     // Add function complete acknowledge with parameter.

}

/* ************************************************************ */
// Declare module
module adder4 {

/* ************************************************************ */
// Internal operation signals

/* ************************************************************ */
// Pallarel equation

/* ************************************************************ */
// Function independent equation
    function    exec {
        done ( A_in + B_in ) ;
    }

}
/* ************************************************************ */

declare ADDER4_func_call {

    input       Add_A_in[4] ;               // Add value input. Port-A
    input       Add_B_in[4] ;               // Add value input. Port-B
    output      Add_result[4] ;             // Add result out

    func_in Add_exec(Add_A_in,Add_B_in) ;   // Add function execution request.
    func_out    Add_done(Add_result) ;

}

module  ADDER4_func_call {
/* ************************************************************ */
// Declare lower module
    adder4      u_adder4 ;  // Declare lower 4bit adder module as "u_adder4"

/* ************************************************************ */
// Internal operation signals

/* ************************************************************ */
// Pallarel equation

/* ************************************************************ */
// Function independent equation
    function    Add_exec {
        Add_done ( u_adder4.exec( Add_A_in, Add_B_in ).Q_out ) ;
        // Declaration
        //  A 'Add_exec' call a 'Add_done' function.
        //  This statement provide 2 parameters with 'exec()' fuction
        //  to lower iniciated 'u_adder4' module.
        //  A result from 'u_adder4' is reflected on 'Q_out'signal.
        //  It send via 'Add_result' pins.
        //
        //  This code shown 'Lower module call', 'Path an input parameter'
        //  and 'Get result' on this single statement.
    }
}
/* ************************************************************ */

Verilog変換例

/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:53:12 2010

 Licensed to :EVALUATION USER:
*/

module adder4 ( p_reset , m_clock , A_in , B_in , Q_out , exec , done );
  input p_reset, m_clock;
  input [3:0] A_in;
  input [3:0] B_in;
  output [3:0] Q_out;
  input exec;
  output done;

   assign  Q_out =
//synthesis translate_off
(exec)?
//synthesis translate_on
((exec)?(A_in)+(B_in):4'b0)
//synthesis translate_off
:4'bx
//synthesis translate_on
;
   assign  done = exec;
endmodule
/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:53:12 2010

 Licensed to
*/

module ADDER4_func_call ( p_reset , m_clock , Add_A_in , Add_B_in , Add_result , Add_exec , Add_done );
  input p_reset, m_clock;
  input [3:0] Add_A_in;
  input [3:0] Add_B_in;
  output [3:0] Add_result;
  input Add_exec;
  output Add_done;
  wire _u_adder4_done;
  wire _u_adder4_exec;
  wire [3:0] _u_adder4_Q_out;
  wire [3:0] _u_adder4_B_in;
  wire [3:0] _u_adder4_A_in;
adder4 u_adder4 (.p_reset(p_reset), .m_clock(m_clock), .done(_u_adder4_done), .exec(_u_adder4_exec), .Q_out(_u_adder4_Q_out), .B_in(_u_adder4_B_in), .A_in(_u_adder4_A_in));

   assign  _u_adder4_exec = Add_exec;
   assign  _u_adder4_B_in =
//synthesis translate_off
(Add_exec)?
//synthesis translate_on
((Add_exec)?Add_B_in:4'b0)
//synthesis translate_off
:4'bx
//synthesis translate_on
;
   assign  _u_adder4_A_in =
//synthesis translate_off
(Add_exec)?
//synthesis translate_on
((Add_exec)?Add_A_in:4'b0)
//synthesis translate_off
:4'bx
//synthesis translate_on
;
   assign  Add_result =
//synthesis translate_off
(Add_exec)?
//synthesis translate_on
((Add_exec)?_u_adder4_Q_out:4'b0)
//synthesis translate_off
:4'bx
//synthesis translate_on
;
   assign  Add_done = Add_exec;
endmodule
/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:53:12 2010

 Licensed to
*/