機能
3入力 AND → OR 複合ゲート
信号機能
A_i = 入力信号A
B_i = 入力信号B
C_i = 入力信号C
Q_o = 出力
記述特徴
NSL記述例
/* ************************************************************ */
declare AOI {
input A_i ;
input B_i ;
input C_i ;
output Q_o ;
}
/* ************************************************************ */
// Declare module
module AOI {
/* ************************************************************ */
// Internal operation signals
/* ************************************************************ */
// Equation
{
Q_o = ( ( A_i & B_i ) | C_i ) ;
}
}
/* ************************************************************ */
Verilog変換例
/*
Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:53:27 2010
Licensed to :EVALUATION USER:
*/
module AOI ( p_reset , m_clock , A_i , B_i , C_i , Q_o );
input p_reset, m_clock;
input A_i;
input B_i;
input C_i;
output Q_o;
assign Q_o = (A_i&B_i)|C_i;
endmodule
/*
Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:53:27 2010
Licensed to
*/