機能

2input OR gate

信号機能

A_i ＝　入力信号

AB_i ＝　入力信号

BQ_o ＝　出力信号

記述特徴

NSL記述例

/* ************************************************************ */
declare OR2 {

    input       A_i ;
    input       B_i ;

    output      Q_o ;

}

/* ************************************************************ */
// Declare module
module OR2 {

/* ************************************************************ */
// Internal operation signals

/* ************************************************************ */
// Equation

    {
        Q_o = ( A_i | B_i ) ;
    }
}
/* ************************************************************ */

Verilog変換例

/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:55:20 2010

 Licensed to :EVALUATION USER:
*/

module OR2 ( p_reset , m_clock , A_i , B_i , Q_o );
  input p_reset, m_clock;
  input A_i;
  input B_i;
  output Q_o;

   assign  Q_o = A_i|B_i;
endmodule
/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:55:20 2010

 Licensed to
*/