UART 受信側
ボーレートジェネレータ：内蔵
データビット長：５・６・７・８，
パリティ選択：パリティ有り無し
パリティ種別：奇数 偶数ビット選択
ストップビット長：1ビット，２ビット
NSL記述例
/*
Input clock frequency is expected to 10.000MHz.
*/
#define TRUE 1'b1
#define FALSE 1'b0
declare UART_Rx {
// Serial receive data input
input RxD_i; // Receiver data input. LSB first
// Parallel receive data output
output Rx_Data_o[8]; // Receiver data in.
func_out RxD_Ready_o() ; // Receiver data read ready flag.
func_out RxD_ParityError_o() ; // Receiver data parity error.
func_out RxD_FramingError_o() ; // Receiver data framing error.
// Command and Status bit
input Freq_Divide_Param_i[16] ;
// Frequency divider parameter for 10.000MHz.
input Rx_BitLength_i[2] ;
// Receiver bit length. 5, 6, 7, and 8.
input Rx_ParityEN_i ;
// Parity enable bit.
// 1 = Parity enable, 0 = Parity disable.
input Rx_OddParity_i ;
// Odd parity bit. 1 = Odd parity, 0 = Even parity.
input Rx_Enable_i ;
// Receiver enable bit. 1 = Enable, 0 = disable
output Rx_operation_o ;
// Receiver function is active.
output Rx_ShiftClock_o ;
// Receiver shift clock. ( for timing check )
}
/*
Input clock frequency is expected to 10.000MHz.
*/
module UART_Rx {
/* ************************************************************ */
/* Declare internal signals */
wire BitLength[4] ;
reg ShiftCount[4] = 0 ;
reg x16_BaudCounter[16] = 0;
reg x16_ShiftTiming = FALSE ;
reg x1_BaudCounter[4] = 0 ;
reg x1_ShiftTiming = FALSE ;
reg Rx_ShiftReg[12] = 0 ; // Parallel -> Serial conversion shift register.
reg internal_RxD_in[3] = 3'b000 ;
wire Rx_Data[8] ;
wire Rx_Parity ; // Parity check node.
reg Detect_StartBit = 0 ;
func_name Receive_Start ;
/* ************************************************************ */
// Procedure description
// Declare function and procedure
proc_name shift_Operation( x1_ShiftTiming, internal_RxD_in ) , //
data_check() , // Parity check & Framing error check
access_complete() ; //
{
/* ************************************************************ */
/* Baud rate generator */
// This function is activate at Rx_Enable_i will be HIGH.
if ( Rx_Enable_i ) {
if ( x16_BaudCounter == Freq_Divide_Param_i ) {
x16_BaudCounter := 16'h0 ; // Reset baud rate counter
x16_ShiftTiming := TRUE ; // and assert Shift Timing indicator.
} else {
x16_BaudCounter := x16_BaudCounter + 16'h1 ; // Count up
x16_ShiftTiming := FALSE ; // Reset Shift Timing indicator.
}
} else {
x16_BaudCounter := 16'h0 ; // Reset baud rate counter
x16_ShiftTiming := FALSE ; // Reset Shift Timing indicator.
}
/* ************************************************************ */
/* Shift timing generation */
// Synchronous INPUT signal and detect center point of START bit.
internal_RxD_in := { internal_RxD_in[1:0] , RxD_i } ; // Clock synchronize and double latch
if ( x16_ShiftTiming ) {
if ( ( internal_RxD_in[2:1] == 2'b00 ) & ~Detect_StartBit ) { // All L level ?
Receive_Start() ; // Detect start bit and operation start.
}
}
if ( Detect_StartBit ) {
if ( x16_ShiftTiming ) {
x1_BaudCounter := x1_BaudCounter + 4'b1 ;
}
} else {
x1_BaudCounter := 4'b0 ;
}
if ( x16_ShiftTiming & x1_BaudCounter == 4'd7 ) {
x1_ShiftTiming := TRUE ; // Assert Shift Timing indicator.
} else {
x1_ShiftTiming := FALSE ; // Reset Shift Timing indicator.
}
/* ************************************************************ */
/* Bit length check */
any {
~Rx_ParityEN_i : any { // without Parity enable
Rx_BitLength_i == 2'b00 : BitLength = 4'd6 ;
// 5bit data length ( Data[4:0] + End )
Rx_BitLength_i == 2'b01 : BitLength = 4'd7 ;
// 6bit data length ( Data[5:0] + End )
Rx_BitLength_i == 2'b10 : BitLength = 4'd8 ;
// 7bit data length ( Data[6:0] + End )
else : BitLength = 4'd9 ;
// 8bit data length ( Data[7:0] + End )
}
else : any { // with Parity enable
Rx_BitLength_i == 2'b00 : BitLength = 4'd7 ;
// 5bit data length ( Data[4:0] + Parity + End )
Rx_BitLength_i == 2'b01 : BitLength = 4'd8 ;
// 6bit data length ( Data[5:0] + Parity + End )
Rx_BitLength_i == 2'b10 : BitLength = 4'd9 ;
// 7bit data length ( Data[6:0] + Parity + End )
else : BitLength = 4'd10;
// 8bit data length ( Data[7:0] + Parity + End )
}
}
/* ************************************************************ */
/* Parity generation */
any {
Rx_OddParity_i : Rx_Parity = ~^(Rx_Data) ; // Calculate ODD parity
else : Rx_Parity = ^(Rx_Data) ; // Calculate EVEN parity
}
/* ************************************************************ */
/* Equation for operation status */
Rx_operation_o = Detect_StartBit ;
Rx_ShiftClock_o = x1_ShiftTiming ;
/* ************************************************************ */
/* Equation for Transmit data output */
any {
~Rx_ParityEN_i : any { // without Parity enable
Rx_BitLength_i == 2'b00 : Rx_Data = { 3#1'b1 , Rx_ShiftReg[10:6] } ;
// output internal shift register value.
Rx_BitLength_i == 2'b01 : Rx_Data = { 2#1'b1 , Rx_ShiftReg[10:5] } ;
// output internal shift register value.
Rx_BitLength_i == 2'b10 : Rx_Data = { 1'b1 , Rx_ShiftReg[10:4] } ;
// output internal shift register value.
else : Rx_Data = Rx_ShiftReg[10:3] ;
// output internal shift register value.
}
else : any { // with Parity enable
Rx_BitLength_i == 2'b00 : Rx_Data = { 3#1'b1 , Rx_ShiftReg[ 9:5] } ;
// output internal shift register value.
Rx_BitLength_i == 2'b01 : Rx_Data = { 2#1'b1 , Rx_ShiftReg[ 9:4] } ;
// output internal shift register value.
Rx_BitLength_i == 2'b10 : Rx_Data = { 1'b1 , Rx_ShiftReg[ 9:3] } ;
// output internal shift register value.
else : Rx_Data = Rx_ShiftReg[ 9:2] ;
// output internal shift register value.
}
}
} // end of equation
/* ************************************************************ */
// Procedure description
function Receive_Start shift_Operation() ;
/* ************************************************************ */
/* Receiver operation */
proc shift_Operation {
Detect_StartBit := TRUE ;
if ( x1_ShiftTiming ) {
// Data capture to shift register
Rx_ShiftReg := { internal_RxD_in[1] , Rx_ShiftReg[11:1] } ;
// Capture synchronized RxD.
// Check bit length counter value
ShiftCount := ShiftCount + 4'b1 ; // Shift counter + 1
if ( ShiftCount == BitLength ) {
data_check() ;
}
}
}
proc data_check { // Parity check
if ( Rx_ParityEN_i & ( Rx_ShiftReg[10] != Rx_Parity ) ) {
// Check parity bit in the Bit<10>
// Assert status flag.
RxD_ParityError_o() ; // Assert ERROR flag.
} else {
if ( Rx_ShiftReg[11] == FALSE ) { // Check stop bit as "1" in the Bit<11>
// Assert status flag.
RxD_FramingError_o() ; // Assert ERROR flag.
} else {
// Assert status flag.
Rx_Data_o = Rx_Data ; // No error and data output
RxD_Ready_o() ; // Assert RECEIVER-READY flag
}
}
access_complete() ;
}
proc access_complete {
// Finish operation
Detect_StartBit := FALSE ;
Rx_ShiftReg := 12'h0 ;
ShiftCount := 4'b0 ;
// Procedure finish.
finish ;
}
/* ************************************************************ */
} // end of moduleVerilog変換例
/*
Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 19:03:52 2010
Licensed to :EVALUATION USER:
*/
module UART_Rx ( p_reset , m_clock , RxD_i , Rx_Data_o , RxD_Ready_o , RxD_ParityError_o , RxD_FramingError_o , Freq_Divide_Param_i , Rx_BitLength_i , Rx_ParityEN_i , Rx_OddParity_i , Rx_Enable_i , Rx_operation_o , Rx_ShiftClock_o );
input p_reset, m_clock;
input RxD_i;
output [7:0] Rx_Data_o;
output RxD_Ready_o;
output RxD_ParityError_o;
output RxD_FramingError_o;
input [15:0] Freq_Divide_Param_i;
input [1:0] Rx_BitLength_i;
input Rx_ParityEN_i;
input Rx_OddParity_i;
input Rx_Enable_i;
output Rx_operation_o;
output Rx_ShiftClock_o;
wire [3:0] BitLength;
reg [3:0] ShiftCount;
reg [15:0] x16_BaudCounter;
reg x16_ShiftTiming;
reg [3:0] x1_BaudCounter;
reg x1_ShiftTiming;
reg [11:0] Rx_ShiftReg;
reg [2:0] internal_RxD_in;
wire [7:0] Rx_Data;
wire Rx_Parity;
reg Detect_StartBit;
wire Receive_Start;
reg shift_Operation;
reg data_check;
reg access_complete;
wire _proc_access_complete_set;
wire _proc_access_complete_reset;
wire _net_0;
wire _proc_data_check_set;
wire _proc_data_check_reset;
wire _net_1;
wire _proc_shift_Operation_set;
wire _proc_shift_Operation_reset;
wire _net_2;
wire _net_3;
wire _net_4;
wire _net_5;
wire _net_6;
wire _net_7;
wire _net_8;
wire _net_9;
wire _net_10;
wire _net_11;
wire _net_12;
wire _net_13;
wire _net_14;
wire _net_15;
wire _net_16;
wire _net_17;
wire _net_18;
wire _net_19;
wire _net_20;
wire _net_21;
wire _net_22;
wire _net_23;
wire _net_24;
wire _net_25;
wire _net_26;
wire _net_27;
wire _net_28;
wire _net_29;
wire _net_30;
wire _net_31;
wire _net_32;
wire _net_33;
wire _net_34;
wire _net_35;
wire _net_36;
wire _net_37;
wire _net_38;
wire _net_39;
wire _net_40;
wire _net_41;
wire _net_42;
wire _net_43;
wire _net_44;
wire _net_45;
wire _net_46;
wire _net_47;
wire _net_48;
wire _net_49;
wire _net_50;
wire _net_51;
wire _net_52;
wire _net_53;
wire _net_54;
wire _net_55;
wire _net_56;
wire _net_57;
assign #1 BitLength = ((_net_30)?4'b1010:4'b0)|
((_net_25|_net_23)?4'b1001:4'b0)|
((_net_22)?4'b0110:4'b0)|
((_net_29|_net_20)?4'b0111:4'b0)|
((_net_27|_net_18)?4'b1000:4'b0);
assign #1 Rx_Data = ((_net_46)?Rx_ShiftReg[9:2]:8'b0)|
((_net_45)?{{{2{1'b1}},1'b1},Rx_ShiftReg[9:5]}:8'b0)|
((_net_43)?{{{1{1'b1}},1'b1},Rx_ShiftReg[9:4]}:8'b0)|
((_net_41)?{1'b1,Rx_ShiftReg[9:3]}:8'b0)|
((_net_39)?Rx_ShiftReg[10:3]:8'b0)|
((_net_38)?{{{2{1'b1}},1'b1},Rx_ShiftReg[10:6]}:8'b0)|
((_net_36)?{{{1{1'b1}},1'b1},Rx_ShiftReg[10:5]}:8'b0)|
((_net_34)?{1'b1,Rx_ShiftReg[10:4]}:8'b0);
assign #1 Rx_Parity = ((_net_31)?^(Rx_Data):1'b0)|
((Rx_OddParity_i)?~(^(Rx_Data)):1'b0);
assign #1 Receive_Start = _net_11;
assign #1 _proc_access_complete_set = data_check;
assign #1 _proc_access_complete_reset = access_complete;
assign #1 _net_0 = _proc_access_complete_set|_proc_access_complete_reset;
assign #1 _proc_data_check_set = _net_51;
assign #1 _proc_data_check_reset = data_check;
assign #1 _net_1 = _proc_data_check_set|_proc_data_check_reset;
assign #1 _proc_shift_Operation_set = Receive_Start;
assign #1 _proc_shift_Operation_reset = _net_50;
assign #1 _net_2 = _proc_shift_Operation_set|_proc_shift_Operation_reset;
assign #1 _net_3 = (x16_BaudCounter)==(Freq_Divide_Param_i);
assign #1 _net_4 = Rx_Enable_i&_net_3;
assign #1 _net_5 = Rx_Enable_i&_net_3;
assign #1 _net_6 = Rx_Enable_i&(~_net_3);
assign #1 _net_7 = Rx_Enable_i&(~_net_3);
assign #1 _net_8 = ~Rx_Enable_i;
assign #1 _net_9 = ~Rx_Enable_i;
assign #1 _net_10 = ((internal_RxD_in[2:1])==(2'b00))&(~Detect_StartBit);
assign #1 _net_11 = x16_ShiftTiming&_net_10;
assign #1 _net_12 = Detect_StartBit&x16_ShiftTiming;
assign #1 _net_13 = ~Detect_StartBit;
assign #1 _net_14 = x16_ShiftTiming&((x1_BaudCounter)==(4'b0111));
assign #1 _net_15 = ~_net_14;
assign #1 _net_16 = ~Rx_ParityEN_i;
assign #1 _net_17 = (Rx_BitLength_i)==(2'b10);
assign #1 _net_18 = _net_16&_net_17;
assign #1 _net_19 = (Rx_BitLength_i)==(2'b01);
assign #1 _net_20 = _net_16&_net_19;
assign #1 _net_21 = (Rx_BitLength_i)==(2'b00);
assign #1 _net_22 = _net_16&_net_21;
assign #1 _net_23 = ((_net_16&(~_net_17))&(~_net_19))&(~_net_21);
assign #1 _net_24 = (Rx_BitLength_i)==(2'b10);
assign #1 _net_25 = (~_net_16)&_net_24;
assign #1 _net_26 = (Rx_BitLength_i)==(2'b01);
assign #1 _net_27 = (~_net_16)&_net_26;
assign #1 _net_28 = (Rx_BitLength_i)==(2'b00);
assign #1 _net_29 = (~_net_16)&_net_28;
assign #1 _net_30 = (((~_net_16)&(~_net_24))&(~_net_26))&(~_net_28);
assign #1 _net_31 = ~Rx_OddParity_i;
assign #1 _net_32 = ~Rx_ParityEN_i;
assign #1 _net_33 = (Rx_BitLength_i)==(2'b10);
assign #1 _net_34 = _net_32&_net_33;
assign #1 _net_35 = (Rx_BitLength_i)==(2'b01);
assign #1 _net_36 = _net_32&_net_35;
assign #1 _net_37 = (Rx_BitLength_i)==(2'b00);
assign #1 _net_38 = _net_32&_net_37;
assign #1 _net_39 = ((_net_32&(~_net_33))&(~_net_35))&(~_net_37);
assign #1 _net_40 = (Rx_BitLength_i)==(2'b10);
assign #1 _net_41 = (~_net_32)&_net_40;
assign #1 _net_42 = (Rx_BitLength_i)==(2'b01);
assign #1 _net_43 = (~_net_32)&_net_42;
assign #1 _net_44 = (Rx_BitLength_i)==(2'b00);
assign #1 _net_45 = (~_net_32)&_net_44;
assign #1 _net_46 = (((~_net_32)&(~_net_40))&(~_net_42))&(~_net_44);
assign #1 _net_47 = shift_Operation&x1_ShiftTiming;
assign #1 _net_48 = shift_Operation&x1_ShiftTiming;
assign #1 _net_49 = (ShiftCount)==(BitLength);
assign #1 _net_50 = (shift_Operation&x1_ShiftTiming)&_net_49;
assign #1 _net_51 = (shift_Operation&x1_ShiftTiming)&_net_49;
assign #1 _net_52 = Rx_ParityEN_i&((Rx_ShiftReg[10])!=(Rx_Parity));
assign #1 _net_53 = data_check&_net_52;
assign #1 _net_54 = (Rx_ShiftReg[11])==(1'b0);
assign #1 _net_55 = (data_check&(~_net_52))&_net_54;
assign #1 _net_56 = (data_check&(~_net_52))&(~_net_54);
assign #1 _net_57 = (data_check&(~_net_52))&(~_net_54);
assign #1 Rx_Data_o = Rx_Data;
assign #1 RxD_Ready_o = _net_57;
assign #1 RxD_ParityError_o = _net_53;
assign #1 RxD_FramingError_o = _net_55;
assign #1 Rx_operation_o = Detect_StartBit;
assign #1 Rx_ShiftClock_o = x1_ShiftTiming;
always @(posedge m_clock or posedge p_reset)
begin
if (p_reset)
ShiftCount <= 4'b0000;
else if ((access_complete)|(_net_48))
ShiftCount <= ((access_complete) ?4'b0000:4'b0)|
((_net_48) ?(ShiftCount)+(4'b0001):4'b0);
end
always @(posedge m_clock or posedge p_reset)
begin
if (p_reset)
x16_BaudCounter <= 16'b0000000000000000;
else if ((_net_6)|(_net_8|_net_4))
x16_BaudCounter <= ((_net_6) ?(x16_BaudCounter)+(16'b0000000000000001):16'b0)|
((_net_8|_net_4) ?16'b0000000000000000:16'b0);
end
always @(posedge m_clock or posedge p_reset)
begin
if (p_reset)
x16_ShiftTiming <= 1'b0;
else if ((_net_9|_net_7)|(_net_5))
x16_ShiftTiming <= ((_net_9|_net_7) ?1'b0:1'b0)|
((_net_5) ?1'b1:1'b0);
end
always @(posedge m_clock or posedge p_reset)
begin
if (p_reset)
x1_BaudCounter <= 4'b0000;
else if ((_net_13)|(_net_12))
x1_BaudCounter <= ((_net_13) ?4'b0000:4'b0)|
((_net_12) ?(x1_BaudCounter)+(4'b0001):4'b0);
end
always @(posedge m_clock or posedge p_reset)
begin
if (p_reset)
x1_ShiftTiming <= 1'b0;
else if ((_net_15)|(_net_14))
x1_ShiftTiming <= ((_net_15) ?1'b0:1'b0)|
((_net_14) ?1'b1:1'b0);
end
always @(posedge m_clock or posedge p_reset)
begin
if (p_reset)
Rx_ShiftReg <= 12'b000000000000;
else if ((access_complete)|(_net_47))
Rx_ShiftReg <= ((access_complete) ?12'b000000000000:12'b0)|
((_net_47) ?{internal_RxD_in[1],Rx_ShiftReg[11:1]}:12'b0);
end
always @(posedge m_clock or posedge p_reset)
begin
if (p_reset)
internal_RxD_in <= 3'b000;
else internal_RxD_in <= {internal_RxD_in[1:0],RxD_i};
end
always @(posedge m_clock or posedge p_reset)
begin
if (p_reset)
Detect_StartBit <= 1'b0;
else if ((access_complete)|(shift_Operation))
Detect_StartBit <= ((access_complete) ?1'b0:1'b0)|
((shift_Operation) ?1'b1:1'b0);
end
always @(posedge m_clock or posedge p_reset)
begin
if (p_reset)
shift_Operation <= 1'b0;
else if ((_net_2))
shift_Operation <= _proc_shift_Operation_set;
end
always @(posedge m_clock or posedge p_reset)
begin
if (p_reset)
data_check <= 1'b0;
else if ((_net_1))
data_check <= _proc_data_check_set;
end
always @(posedge m_clock or posedge p_reset)
begin
if (p_reset)
access_complete <= 1'b0;
else if ((_net_0))
access_complete <= _proc_access_complete_set;
end
endmodule
/*
Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 19:03:52 2010
Licensed to
*/