UART 送信側

ボーレートジェネレータ：内蔵

データビット長：５・６・７・８，

パリティ選択：パリティ有り無し

パリティ種別：奇数　偶数ビット選択

ストップビット長：1ビット，２ビット

NSL記述例

/*

    Input clock frequency is expected to 10.000MHz.

*/

#define     TRUE    1'b1
#define     FALSE   1'b0

declare     UART_Tx     {
// Transmit data input
    input       Tx_Data_i[8];               // Transmit data in.

// Transmit data output
    output      TxD_o;                      // Transmit data out. LSB first

    // Command and Status bit
    input       Freq_Divide_Param_i[16] ;
                // Frequency divider parameter for 10.000MHz.
    input       Tx_BitLength_i[2] ;
                // Transmit bit length. 5, 6, 7, and 8.
    input       Tx_ParityEN_i ;
                // Parity enable bit. 1 = Parity enable, 0 = Parity disable.
    input       Tx_OddParity_i ;
                // Odd parity bit. 1 = Odd parity, 0 = Even parity.
    input       Tx_Enable_i ;
                // Transmit enable bit. 1 = Enable, 0 = disable

    output      Tx_Ready_o ;
                // Transmit ready flag.
    output      Tx_ShiftClock_o ;
                // Transmit shift clock. ( for timing check )

// Control signals
    func_in     Tx_Start_i ;
                // Transmit start request.
    func_out    Tx_Finish_o ;
                // Transmit finish acknowledge.
}

/*

    Input clock frequency is expected to 10.000MHz.

*/


module UART_Tx {
/* ************************************************************ */
/* Declare internal signals */
    wire    BitLength[4] ;

    reg     ShiftCount[4] = 0 ;

    reg     BaudCounter[20] = 0 ;
    reg     ShiftTiming = 0 ;

    reg     Tx_ShiftReg[12] = 0 ;               // Parallel -> Serial conversion shift register.
    reg     internal_TxD_out = TRUE ;

    wire    Tx_Parity ;

    reg     internal_READY = TRUE ;

/* ************************************************************ */
// Procedure description
//      Declare function and procedure 

    proc_name   capture_TxData() ,                                      //
                shift_Operation( Tx_ShiftReg ) ,                        //
                access_complete() ;                                     //

{
/* ************************************************************ */
/* Baud rate generator */
//   This function is activate at Tx_Enable_i will be HIGH.
    if ( Tx_Enable_i ) {
        if ( BaudCounter == { Freq_Divide_Param_i , 4'b1111 } ) {
            BaudCounter := 20'h0 ;                  // Reset baud rate counter
            ShiftTiming := TRUE ;                   //  and assert Shift Timing indicator.
        } else {
            BaudCounter := BaudCounter + 20'b1 ;    // Count up
            ShiftTiming := FALSE ;
        }
    } else {
        BaudCounter := 20'h0 ;                      // Reset baud rate counter
        ShiftTiming := FALSE ;                      // Reset Shift Timing indicator.
    }

/* ************************************************************ */
/* Bit length check */
    any {
        ~Tx_ParityEN_i  : any {         //  without Parity enable
            Tx_BitLength_i == 2'b00 : BitLength = 4'd7 ;
                                        //    5bit data length ( Start + Data[4:0] + End )
            Tx_BitLength_i == 2'b01 : BitLength = 4'd8 ;
                                        //    6bit data length ( Start + Data[5:0] + End )
            Tx_BitLength_i == 2'b10 : BitLength = 4'd9 ;
                                        //    7bit data length ( Start + Data[6:0] + End )
            else                    : BitLength = 4'd10;
                                        //    8bit data length ( Start + Data[7:0] + End )
        }
        else            : any {         // with Parity enable
            Tx_BitLength_i == 2'b00 : BitLength = 4'd8 ;
                                        //    5bit data length ( Start + Data[4:0] + Parity + End )
            Tx_BitLength_i == 2'b01 : BitLength = 4'd9 ;
                                        //    6bit data length ( Start + Data[5:0] + Parity + End )
            Tx_BitLength_i == 2'b10 : BitLength = 4'd10;
                                        //    7bit data length ( Start + Data[6:0] + Parity + End )
            else                    : BitLength = 4'd11;
                                        //    8bit data length ( Start + Data[7:0] + Parity + End )
        }
    }

/* ************************************************************ */
/* Parity generation */
    any {
        Tx_OddParity_i  : Tx_Parity = ~^(Tx_Data_i) ;           // Calculate ODD parity
        else            : Tx_Parity =  ^(Tx_Data_i) ;           // Calculate EVEN parity
    }

/* ************************************************************ */
/* Equation for Transmit data output */
    TxD_o           = internal_TxD_out ;    // output internal shift register value.
    Tx_Ready_o      = internal_READY ;
    Tx_ShiftClock_o = ShiftTiming ;

}   // end of equation

/* ************************************************************ */
// Procedure description
    function    Tx_Start_i      capture_TxData() ;

/* ************************************************************ */
/* Transmit operation */
    proc    capture_TxData {
    // Invalidate READY flag
        internal_READY := FALSE ;

    // Set TxD output pin level
        internal_TxD_out := TRUE ;                              // H-level reset.

    // Initialize shift counter
        ShiftCount := 4'd0 ;

    // Generate Shift register value.
        any {
        // 5bit length
            Tx_BitLength_i == 2'b00 : {
                if ( Tx_ParityEN_i ) {                          //  with Parity enable
                    shift_Operation( { 5#TRUE , Tx_Parity , Tx_Data_i[4:0] , FALSE } ) ;
                } else {                                        //  without Parity enable
                    shift_Operation( { 5#TRUE , 1'b1      , Tx_Data_i[4:0] , FALSE } ) ;
                }
            }
        // 6bit length
            Tx_BitLength_i == 2'b01 : {
                if ( Tx_ParityEN_i ) {                          //  with Parity enable
                    shift_Operation( { 4#TRUE , Tx_Parity , Tx_Data_i[5:0] , FALSE } ) ;
                } else {                                        //  without Parity enable
                    shift_Operation( { 4#TRUE , 1'b1      , Tx_Data_i[5:0] , FALSE } ) ;
                }
            }
        // 7bit length
            Tx_BitLength_i == 2'b10 : {
                if ( Tx_ParityEN_i ) {                          //  with Parity enable
                    shift_Operation( { 3#TRUE , Tx_Parity , Tx_Data_i[6:0] , FALSE } ) ;
                } else {                                        //  without Parity enable
                    shift_Operation( { 3#TRUE , 1'b1      , Tx_Data_i[6:0] , FALSE } ) ;
                }
            }
        // 8bit length
            else : {
                if ( Tx_ParityEN_i ) {                          //  with Parity enable
                    shift_Operation( { 2#TRUE , Tx_Parity , Tx_Data_i[7:0] , FALSE } ) ;
                } else {                                        //  without Parity enable
                    shift_Operation( { 2#TRUE , 1'b1      , Tx_Data_i[7:0] , FALSE } ) ;
                }
            }
        }
    }

    proc    shift_Operation {
        if ( ShiftTiming ) {
        // Equation for shift register operation.
            Tx_ShiftReg := { TRUE , Tx_ShiftReg[11:1] } ;       // Shift operation
            internal_TxD_out := Tx_ShiftReg[0] ;                // Data output

        // Bit length check
            ShiftCount := ShiftCount + 4'd1 ;
            if ( ShiftCount == BitLength ) {
                access_complete() ;
            }
        }
    }       

    proc    access_complete {
    // Assert status flag.
        Tx_Finish_o() ;
        internal_READY := TRUE ;

    // Procedure finish.
        finish ;
    }

/* ************************************************************ */
}   // end of module

Verilog変換例

/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 19:03:13 2010

 Licensed to :EVALUATION USER:
*/

module UART_Tx ( p_reset , m_clock , Tx_Data_i , TxD_o , Freq_Divide_Param_i , Tx_BitLength_i , Tx_ParityEN_i , Tx_OddParity_i , Tx_Enable_i , Tx_Ready_o , Tx_ShiftClock_o , Tx_Start_i , Tx_Finish_o );
  input p_reset, m_clock;
  input [7:0] Tx_Data_i;
  output TxD_o;
  input [15:0] Freq_Divide_Param_i;
  input [1:0] Tx_BitLength_i;
  input Tx_ParityEN_i;
  input Tx_OddParity_i;
  input Tx_Enable_i;
  output Tx_Ready_o;
  output Tx_ShiftClock_o;
  input Tx_Start_i;
  output Tx_Finish_o;
  wire [3:0] BitLength;
  reg [3:0] ShiftCount;
  reg [19:0] BaudCounter;
  reg ShiftTiming;
  reg [11:0] Tx_ShiftReg;
  reg internal_TxD_out;
  wire Tx_Parity;
  reg internal_READY;
  reg capture_TxData;
  reg shift_Operation;
  reg access_complete;
  wire _proc_access_complete_set;
  wire _proc_access_complete_reset;
  wire _net_0;
  wire _proc_shift_Operation_set;
  wire _proc_shift_Operation_reset;
  wire _net_1;
  wire _proc_capture_TxData_set;
  wire _proc_capture_TxData_reset;
  wire _net_2;
  wire _net_3;
  wire _net_4;
  wire _net_5;
  wire _net_6;
  wire _net_7;
  wire _net_8;
  wire _net_9;
  wire _net_10;
  wire _net_11;
  wire _net_12;
  wire _net_13;
  wire _net_14;
  wire _net_15;
  wire _net_16;
  wire _net_17;
  wire _net_18;
  wire _net_19;
  wire _net_20;
  wire _net_21;
  wire _net_22;
  wire _net_23;
  wire _net_24;
  wire _net_25;
  wire _net_26;
  wire _net_27;
  wire _net_28;
  wire _net_29;
  wire _net_30;
  wire _net_31;
  wire _net_32;
  wire _net_33;
  wire _net_34;
  wire _net_35;
  wire _net_36;
  wire _net_37;
  wire _net_38;
  wire _net_39;
  wire _net_40;
  wire _net_41;
  wire _net_42;
  wire _net_43;
  wire _net_44;
  wire _net_45;
  wire _net_46;
  wire _net_47;
  wire _net_48;
  wire _net_49;
  wire _net_50;
  wire _net_51;
  wire _net_52;
  wire _net_53;
  wire _net_54;
  wire _net_55;
  wire _net_56;
  wire _net_57;
  wire _net_58;

   assign #1 BitLength = ((_net_24)?4'b1011:4'b0)|
    ((_net_19|_net_17)?4'b1010:4'b0)|
    ((_net_16)?4'b0111:4'b0)|
    ((_net_23|_net_14)?4'b1000:4'b0)|
    ((_net_21|_net_12)?4'b1001:4'b0);
   assign #1 Tx_Parity = ((_net_25)?^(Tx_Data_i):1'b0)|
    ((Tx_OddParity_i)?~(^(Tx_Data_i)):1'b0);
   assign #1 _proc_access_complete_set = _net_58;
   assign #1 _proc_access_complete_reset = access_complete;
   assign #1 _net_0 = _proc_access_complete_set|_proc_access_complete_reset;
   assign #1 _proc_shift_Operation_set = _net_51|_net_48|_net_45|_net_42|_net_38|_net_35|_net_31|_net_28;
   assign #1 _proc_shift_Operation_reset = _net_57;
   assign #1 _net_1 = _proc_shift_Operation_set|_proc_shift_Operation_reset;
   assign #1 _proc_capture_TxData_set = Tx_Start_i;
   assign #1 _proc_capture_TxData_reset = _net_50|_net_47|_net_44|_net_41|_net_37|_net_34|_net_30|_net_27;
   assign #1 _net_2 = _proc_capture_TxData_set|_proc_capture_TxData_reset;
   assign #1 _net_3 = (BaudCounter)==({Freq_Divide_Param_i,4'b1111});
   assign #1 _net_4 = Tx_Enable_i&_net_3;
   assign #1 _net_5 = Tx_Enable_i&_net_3;
   assign #1 _net_6 = Tx_Enable_i&(~_net_3);
   assign #1 _net_7 = Tx_Enable_i&(~_net_3);
   assign #1 _net_8 = ~Tx_Enable_i;
   assign #1 _net_9 = ~Tx_Enable_i;
   assign #1 _net_10 = ~Tx_ParityEN_i;
   assign #1 _net_11 = (Tx_BitLength_i)==(2'b10);
   assign #1 _net_12 = _net_10&_net_11;
   assign #1 _net_13 = (Tx_BitLength_i)==(2'b01);
   assign #1 _net_14 = _net_10&_net_13;
   assign #1 _net_15 = (Tx_BitLength_i)==(2'b00);
   assign #1 _net_16 = _net_10&_net_15;
   assign #1 _net_17 = ((_net_10&(~_net_11))&(~_net_13))&(~_net_15);
   assign #1 _net_18 = (Tx_BitLength_i)==(2'b10);
   assign #1 _net_19 = (~_net_10)&_net_18;
   assign #1 _net_20 = (Tx_BitLength_i)==(2'b01);
   assign #1 _net_21 = (~_net_10)&_net_20;
   assign #1 _net_22 = (Tx_BitLength_i)==(2'b00);
   assign #1 _net_23 = (~_net_10)&_net_22;
   assign #1 _net_24 = (((~_net_10)&(~_net_18))&(~_net_20))&(~_net_22);
   assign #1 _net_25 = ~Tx_OddParity_i;
   assign #1 _net_26 = (Tx_BitLength_i)==(2'b10);
   assign #1 _net_27 = (capture_TxData&_net_26)&Tx_ParityEN_i;
   assign #1 _net_28 = (capture_TxData&_net_26)&Tx_ParityEN_i;
   assign #1 _net_29 = (capture_TxData&_net_26)&Tx_ParityEN_i;
   assign #1 _net_30 = (capture_TxData&_net_26)&(~Tx_ParityEN_i);
   assign #1 _net_31 = (capture_TxData&_net_26)&(~Tx_ParityEN_i);
   assign #1 _net_32 = (capture_TxData&_net_26)&(~Tx_ParityEN_i);
   assign #1 _net_33 = (Tx_BitLength_i)==(2'b01);
   assign #1 _net_34 = (capture_TxData&_net_33)&Tx_ParityEN_i;
   assign #1 _net_35 = (capture_TxData&_net_33)&Tx_ParityEN_i;
   assign #1 _net_36 = (capture_TxData&_net_33)&Tx_ParityEN_i;
   assign #1 _net_37 = (capture_TxData&_net_33)&(~Tx_ParityEN_i);
   assign #1 _net_38 = (capture_TxData&_net_33)&(~Tx_ParityEN_i);
   assign #1 _net_39 = (capture_TxData&_net_33)&(~Tx_ParityEN_i);
   assign #1 _net_40 = (Tx_BitLength_i)==(2'b00);
   assign #1 _net_41 = (capture_TxData&_net_40)&Tx_ParityEN_i;
   assign #1 _net_42 = (capture_TxData&_net_40)&Tx_ParityEN_i;
   assign #1 _net_43 = (capture_TxData&_net_40)&Tx_ParityEN_i;
   assign #1 _net_44 = (capture_TxData&_net_40)&(~Tx_ParityEN_i);
   assign #1 _net_45 = (capture_TxData&_net_40)&(~Tx_ParityEN_i);
   assign #1 _net_46 = (capture_TxData&_net_40)&(~Tx_ParityEN_i);
   assign #1 _net_47 = (((capture_TxData&(~_net_26))&(~_net_33))&(~_net_40))&Tx_ParityEN_i;
   assign #1 _net_48 = (((capture_TxData&(~_net_26))&(~_net_33))&(~_net_40))&Tx_ParityEN_i;
   assign #1 _net_49 = (((capture_TxData&(~_net_26))&(~_net_33))&(~_net_40))&Tx_ParityEN_i;
   assign #1 _net_50 = (((capture_TxData&(~_net_26))&(~_net_33))&(~_net_40))&(~Tx_ParityEN_i);
   assign #1 _net_51 = (((capture_TxData&(~_net_26))&(~_net_33))&(~_net_40))&(~Tx_ParityEN_i);
   assign #1 _net_52 = (((capture_TxData&(~_net_26))&(~_net_33))&(~_net_40))&(~Tx_ParityEN_i);
   assign #1 _net_53 = shift_Operation&ShiftTiming;
   assign #1 _net_54 = shift_Operation&ShiftTiming;
   assign #1 _net_55 = shift_Operation&ShiftTiming;
   assign #1 _net_56 = (ShiftCount)==(BitLength);
   assign #1 _net_57 = (shift_Operation&ShiftTiming)&_net_56;
   assign #1 _net_58 = (shift_Operation&ShiftTiming)&_net_56;
   assign #1 TxD_o = internal_TxD_out;
   assign #1 Tx_Ready_o = internal_READY;
   assign #1 Tx_ShiftClock_o = ShiftTiming;
   assign #1 Tx_Finish_o = access_complete;
always @(posedge m_clock or posedge p_reset)
  begin
if (p_reset)
     ShiftCount <= 4'b0000;
else if ((_net_55)|(capture_TxData))
      ShiftCount <= ((_net_55) ?(ShiftCount)+(4'b0001):4'b0)|
    ((capture_TxData) ?4'b0000:4'b0);

end
always @(posedge m_clock or posedge p_reset)
  begin
if (p_reset)
     BaudCounter <= 20'b00000000000000000000;
else if ((_net_6)|(_net_8|_net_4))
      BaudCounter <= ((_net_6) ?(BaudCounter)+(20'b00000000000000000001):20'b0)|
    ((_net_8|_net_4) ?20'b00000000000000000000:20'b0);

end
always @(posedge m_clock or posedge p_reset)
  begin
if (p_reset)
     ShiftTiming <= 1'b0;
else if ((_net_9|_net_7)|(_net_5))
      ShiftTiming <= ((_net_9|_net_7) ?1'b0:1'b0)|
    ((_net_5) ?1'b1:1'b0);

end
always @(posedge m_clock or posedge p_reset)
  begin
if (p_reset)
     Tx_ShiftReg <= 12'b000000000000;
else if ((_net_53)|(_net_52)|(_net_49)|(_net_46)|(_net_43)|(_net_39)|(_net_36)|(_net_32)|(_net_29))
      Tx_ShiftReg <= ((_net_53) ?{1'b1,Tx_ShiftReg[11:1]}:12'b0)|
    ((_net_52) ?{{{1{1'b1}},1'b1},1'b1,Tx_Data_i[7:0],1'b0}:12'b0)|
    ((_net_49) ?{{{1{1'b1}},1'b1},Tx_Parity,Tx_Data_i[7:0],1'b0}:12'b0)|
    ((_net_46) ?{{{4{1'b1}},1'b1},1'b1,Tx_Data_i[4:0],1'b0}:12'b0)|
    ((_net_43) ?{{{4{1'b1}},1'b1},Tx_Parity,Tx_Data_i[4:0],1'b0}:12'b0)|
    ((_net_39) ?{{{3{1'b1}},1'b1},1'b1,Tx_Data_i[5:0],1'b0}:12'b0)|
    ((_net_36) ?{{{3{1'b1}},1'b1},Tx_Parity,Tx_Data_i[5:0],1'b0}:12'b0)|
    ((_net_32) ?{{{2{1'b1}},1'b1},1'b1,Tx_Data_i[6:0],1'b0}:12'b0)|
    ((_net_29) ?{{{2{1'b1}},1'b1},Tx_Parity,Tx_Data_i[6:0],1'b0}:12'b0);

end
always @(posedge m_clock or posedge p_reset)
  begin
if (p_reset)
     internal_TxD_out <= 1'b1;
else if ((_net_54)|(capture_TxData))
      internal_TxD_out <= ((_net_54) ?Tx_ShiftReg[0]:1'b0)|
    ((capture_TxData) ?1'b1:1'b0);

end
always @(posedge m_clock or posedge p_reset)
  begin
if (p_reset)
     internal_READY <= 1'b1;
else if ((access_complete)|(capture_TxData))
      internal_READY <= ((access_complete) ?1'b1:1'b0)|
    ((capture_TxData) ?1'b0:1'b0);

end
always @(posedge m_clock or posedge p_reset)
  begin
if (p_reset)
     capture_TxData <= 1'b0;
else if ((_net_2))
      capture_TxData <= _proc_capture_TxData_set;
end
always @(posedge m_clock or posedge p_reset)
  begin
if (p_reset)
     shift_Operation <= 1'b0;
else if ((_net_1))
      shift_Operation <= _proc_shift_Operation_set;
end
always @(posedge m_clock or posedge p_reset)
  begin
if (p_reset)
     access_complete <= 1'b0;
else if ((_net_0))
      access_complete <= _proc_access_complete_set;
end
endmodule
/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 19:03:13 2010

 Licensed to
*/